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arch-ia64.h
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1 /*-------------------------------------------------------------------------
2  *
3  * arch-ia64.h
4  * Atomic operations considerations specific to intel itanium
5  *
6  * Portions Copyright (c) 1996-2017, PostgreSQL Global Development Group
7  * Portions Copyright (c) 1994, Regents of the University of California
8  *
9  * NOTES:
10  *
11  * src/include/port/atomics/arch-ia64.h
12  *
13  *-------------------------------------------------------------------------
14  */
15 
16 /*
17  * Itanium is weakly ordered, so read and write barriers require a full
18  * fence.
19  */
20 #if defined(__INTEL_COMPILER)
21 # define pg_memory_barrier_impl() __mf()
22 #elif defined(__GNUC__)
23 # define pg_memory_barrier_impl() __asm__ __volatile__ ("mf" : : : "memory")
24 #elif defined(__hpux)
25 # define pg_memory_barrier_impl() _Asm_mf()
26 #endif
27 
28 /* per architecture manual doubleword accesses have single copy atomicity */
29 #define PG_HAVE_8BYTE_SINGLE_COPY_ATOMICITY