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generic-acc.h
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1 /*-------------------------------------------------------------------------
2  *
3  * generic-acc.h
4  * Atomic operations support when using HPs acc on HPUX
5  *
6  * Portions Copyright (c) 1996-2017, PostgreSQL Global Development Group
7  * Portions Copyright (c) 1994, Regents of the University of California
8  *
9  * NOTES:
10  *
11  * Documentation:
12  * * inline assembly for Itanium-based HP-UX:
13  * http://h21007.www2.hp.com/portal/download/files/unprot/Itanium/inline_assem_ERS.pdf
14  * * Implementing Spinlocks on the Intel (R) Itanium (R) Architecture and PA-RISC
15  * http://h21007.www2.hp.com/portal/download/files/unprot/itanium/spinlocks.pdf
16  *
17  * Itanium only supports a small set of numbers (6, -8, -4, -1, 1, 4, 8, 16)
18  * for atomic add/sub, so we just implement everything but compare_exchange
19  * via the compare_exchange fallbacks in atomics/generic.h.
20  *
21  * src/include/port/atomics/generic-acc.h
22  *
23  * -------------------------------------------------------------------------
24  */
25 
26 #include <machine/sys/inline.h>
27 
28 #define pg_compiler_barrier_impl() _Asm_sched_fence()
29 
30 #if defined(HAVE_ATOMICS)
31 
32 /* IA64 always has 32/64 bit atomics */
33 
34 #define PG_HAVE_ATOMIC_U32_SUPPORT
35 typedef struct pg_atomic_uint32
36 {
37  volatile uint32 value;
39 
40 #define PG_HAVE_ATOMIC_U64_SUPPORT
41 typedef struct pg_atomic_uint64
42 {
43  /*
44  * Alignment is guaranteed to be 64bit. Search for "Well-behaved
45  * application restrictions" => "Data alignment and data sharing" on HP's
46  * website. Unfortunately the URL doesn't seem to stable enough to
47  * include.
48  */
49  volatile uint64 value;
51 
52 
53 #define MINOR_FENCE (_Asm_fence) (_UP_CALL_FENCE | _UP_SYS_FENCE | \
54  _DOWN_CALL_FENCE | _DOWN_SYS_FENCE )
55 
56 #define PG_HAVE_ATOMIC_COMPARE_EXCHANGE_U32
57 static inline bool
59  uint32 *expected, uint32 newval)
60 {
61  bool ret;
62  uint32 current;
63 
64  _Asm_mov_to_ar(_AREG_CCV, *expected, MINOR_FENCE);
65  /*
66  * We want a barrier, not just release/acquire semantics.
67  */
68  _Asm_mf();
69  /*
70  * Notes:
71  * DOWN_MEM_FENCE | _UP_MEM_FENCE prevents reordering by the compiler
72  */
73  current = _Asm_cmpxchg(_SZ_W, /* word */
74  _SEM_REL,
75  &ptr->value,
76  newval, _LDHINT_NONE,
77  _DOWN_MEM_FENCE | _UP_MEM_FENCE);
78  ret = current == *expected;
79  *expected = current;
80  return ret;
81 }
82 
83 
84 #define PG_HAVE_ATOMIC_COMPARE_EXCHANGE_U64
85 static inline bool
87  uint64 *expected, uint64 newval)
88 {
89  bool ret;
90  uint64 current;
91 
92  _Asm_mov_to_ar(_AREG_CCV, *expected, MINOR_FENCE);
93  _Asm_mf();
94  current = _Asm_cmpxchg(_SZ_D, /* doubleword */
95  _SEM_REL,
96  &ptr->value,
97  newval, _LDHINT_NONE,
98  _DOWN_MEM_FENCE | _UP_MEM_FENCE);
99  ret = current == *expected;
100  *expected = current;
101  return ret;
102 }
103 
104 #undef MINOR_FENCE
105 
106 #endif /* defined(HAVE_ATOMICS) */
struct pg_atomic_uint32 pg_atomic_uint32
bool pg_atomic_compare_exchange_u64_impl(volatile pg_atomic_uint64 *ptr, uint64 *expected, uint64 newval)
Definition: atomics.c:183
struct pg_atomic_uint64 pg_atomic_uint64
bool pg_atomic_compare_exchange_u32_impl(volatile pg_atomic_uint32 *ptr, uint32 *expected, uint32 newval)
Definition: atomics.c:120
volatile uint32 value
Definition: fallback.h:100
unsigned int uint32
Definition: c.h:268
volatile uint64 value
Definition: fallback.h:118
#define newval