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s_lock.h
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1 /*-------------------------------------------------------------------------
2  *
3  * s_lock.h
4  * Hardware-dependent implementation of spinlocks.
5  *
6  * NOTE: none of the macros in this file are intended to be called directly.
7  * Call them through the hardware-independent macros in spin.h.
8  *
9  * The following hardware-dependent macros must be provided for each
10  * supported platform:
11  *
12  * void S_INIT_LOCK(slock_t *lock)
13  * Initialize a spinlock (to the unlocked state).
14  *
15  * int S_LOCK(slock_t *lock)
16  * Acquire a spinlock, waiting if necessary.
17  * Time out and abort() if unable to acquire the lock in a
18  * "reasonable" amount of time --- typically ~ 1 minute.
19  * Should return number of "delays"; see s_lock.c
20  *
21  * void S_UNLOCK(slock_t *lock)
22  * Unlock a previously acquired lock.
23  *
24  * bool S_LOCK_FREE(slock_t *lock)
25  * Tests if the lock is free. Returns true if free, false if locked.
26  * This does *not* change the state of the lock.
27  *
28  * void SPIN_DELAY(void)
29  * Delay operation to occur inside spinlock wait loop.
30  *
31  * Note to implementors: there are default implementations for all these
32  * macros at the bottom of the file. Check if your platform can use
33  * these or needs to override them.
34  *
35  * Usually, S_LOCK() is implemented in terms of even lower-level macros
36  * TAS() and TAS_SPIN():
37  *
38  * int TAS(slock_t *lock)
39  * Atomic test-and-set instruction. Attempt to acquire the lock,
40  * but do *not* wait. Returns 0 if successful, nonzero if unable
41  * to acquire the lock.
42  *
43  * int TAS_SPIN(slock_t *lock)
44  * Like TAS(), but this version is used when waiting for a lock
45  * previously found to be contended. By default, this is the
46  * same as TAS(), but on some architectures it's better to poll a
47  * contended lock using an unlocked instruction and retry the
48  * atomic test-and-set only when it appears free.
49  *
50  * TAS() and TAS_SPIN() are NOT part of the API, and should never be called
51  * directly.
52  *
53  * CAUTION: on some platforms TAS() and/or TAS_SPIN() may sometimes report
54  * failure to acquire a lock even when the lock is not locked. For example,
55  * on Alpha TAS() will "fail" if interrupted. Therefore a retry loop must
56  * always be used, even if you are certain the lock is free.
57  *
58  * It is the responsibility of these macros to make sure that the compiler
59  * does not re-order accesses to shared memory to precede the actual lock
60  * acquisition, or follow the lock release. Prior to PostgreSQL 9.5, this
61  * was the caller's responsibility, which meant that callers had to use
62  * volatile-qualified pointers to refer to both the spinlock itself and the
63  * shared data being accessed within the spinlocked critical section. This
64  * was notationally awkward, easy to forget (and thus error-prone), and
65  * prevented some useful compiler optimizations. For these reasons, we
66  * now require that the macros themselves prevent compiler re-ordering,
67  * so that the caller doesn't need to take special precautions.
68  *
69  * On platforms with weak memory ordering, the TAS(), TAS_SPIN(), and
70  * S_UNLOCK() macros must further include hardware-level memory fence
71  * instructions to prevent similar re-ordering at the hardware level.
72  * TAS() and TAS_SPIN() must guarantee that loads and stores issued after
73  * the macro are not executed until the lock has been obtained. Conversely,
74  * S_UNLOCK() must guarantee that loads and stores issued before the macro
75  * have been executed before the lock is released.
76  *
77  * On most supported platforms, TAS() uses a tas() function written
78  * in assembly language to execute a hardware atomic-test-and-set
79  * instruction. Equivalent OS-supplied mutex routines could be used too.
80  *
81  * If no system-specific TAS() is available (ie, HAVE_SPINLOCKS is not
82  * defined), then we fall back on an emulation that uses SysV semaphores
83  * (see spin.c). This emulation will be MUCH MUCH slower than a proper TAS()
84  * implementation, because of the cost of a kernel call per lock or unlock.
85  * An old report is that Postgres spends around 40% of its time in semop(2)
86  * when using the SysV semaphore code.
87  *
88  *
89  * Portions Copyright (c) 1996-2022, PostgreSQL Global Development Group
90  * Portions Copyright (c) 1994, Regents of the University of California
91  *
92  * src/include/storage/s_lock.h
93  *
94  *-------------------------------------------------------------------------
95  */
96 #ifndef S_LOCK_H
97 #define S_LOCK_H
98 
99 #ifdef FRONTEND
100 #error "s_lock.h may not be included from frontend code"
101 #endif
102 
103 #ifdef HAVE_SPINLOCKS /* skip spinlocks if requested */
104 
105 #if defined(__GNUC__) || defined(__INTEL_COMPILER)
106 /*************************************************************************
107  * All the gcc inlines
108  * Gcc consistently defines the CPU as __cpu__.
109  * Other compilers use __cpu or __cpu__ so we test for both in those cases.
110  */
111 
112 /*----------
113  * Standard gcc asm format (assuming "volatile slock_t *lock"):
114 
115  __asm__ __volatile__(
116  " instruction \n"
117  " instruction \n"
118  " instruction \n"
119 : "=r"(_res), "+m"(*lock) // return register, in/out lock value
120 : "r"(lock) // lock pointer, in input register
121 : "memory", "cc"); // show clobbered registers here
122 
123  * The output-operands list (after first colon) should always include
124  * "+m"(*lock), whether or not the asm code actually refers to this
125  * operand directly. This ensures that gcc believes the value in the
126  * lock variable is used and set by the asm code. Also, the clobbers
127  * list (after third colon) should always include "memory"; this prevents
128  * gcc from thinking it can cache the values of shared-memory fields
129  * across the asm code. Add "cc" if your asm code changes the condition
130  * code register, and also list any temp registers the code uses.
131  *----------
132  */
133 
134 
135 #ifdef __i386__ /* 32-bit i386 */
136 #define HAS_TEST_AND_SET
137 
138 typedef unsigned char slock_t;
139 
140 #define TAS(lock) tas(lock)
141 
142 static __inline__ int
143 tas(volatile slock_t *lock)
144 {
145  register slock_t _res = 1;
146 
147  /*
148  * Use a non-locking test before asserting the bus lock. Note that the
149  * extra test appears to be a small loss on some x86 platforms and a small
150  * win on others; it's by no means clear that we should keep it.
151  *
152  * When this was last tested, we didn't have separate TAS() and TAS_SPIN()
153  * macros. Nowadays it probably would be better to do a non-locking test
154  * in TAS_SPIN() but not in TAS(), like on x86_64, but no-one's done the
155  * testing to verify that. Without some empirical evidence, better to
156  * leave it alone.
157  */
158  __asm__ __volatile__(
159  " cmpb $0,%1 \n"
160  " jne 1f \n"
161  " lock \n"
162  " xchgb %0,%1 \n"
163  "1: \n"
164 : "+q"(_res), "+m"(*lock)
165 : /* no inputs */
166 : "memory", "cc");
167  return (int) _res;
168 }
169 
170 #define SPIN_DELAY() spin_delay()
171 
172 static __inline__ void
173 spin_delay(void)
174 {
175  /*
176  * This sequence is equivalent to the PAUSE instruction ("rep" is
177  * ignored by old IA32 processors if the following instruction is
178  * not a string operation); the IA-32 Architecture Software
179  * Developer's Manual, Vol. 3, Section 7.7.2 describes why using
180  * PAUSE in the inner loop of a spin lock is necessary for good
181  * performance:
182  *
183  * The PAUSE instruction improves the performance of IA-32
184  * processors supporting Hyper-Threading Technology when
185  * executing spin-wait loops and other routines where one
186  * thread is accessing a shared lock or semaphore in a tight
187  * polling loop. When executing a spin-wait loop, the
188  * processor can suffer a severe performance penalty when
189  * exiting the loop because it detects a possible memory order
190  * violation and flushes the core processor's pipeline. The
191  * PAUSE instruction provides a hint to the processor that the
192  * code sequence is a spin-wait loop. The processor uses this
193  * hint to avoid the memory order violation and prevent the
194  * pipeline flush. In addition, the PAUSE instruction
195  * de-pipelines the spin-wait loop to prevent it from
196  * consuming execution resources excessively.
197  */
198  __asm__ __volatile__(
199  " rep; nop \n");
200 }
201 
202 #endif /* __i386__ */
203 
204 
205 #ifdef __x86_64__ /* AMD Opteron, Intel EM64T */
206 #define HAS_TEST_AND_SET
207 
208 typedef unsigned char slock_t;
209 
210 #define TAS(lock) tas(lock)
211 
212 /*
213  * On Intel EM64T, it's a win to use a non-locking test before the xchg proper,
214  * but only when spinning.
215  *
216  * See also Implementing Scalable Atomic Locks for Multi-Core Intel(tm) EM64T
217  * and IA32, by Michael Chynoweth and Mary R. Lee. As of this writing, it is
218  * available at:
219  * http://software.intel.com/en-us/articles/implementing-scalable-atomic-locks-for-multi-core-intel-em64t-and-ia32-architectures
220  */
221 #define TAS_SPIN(lock) (*(lock) ? 1 : TAS(lock))
222 
223 static __inline__ int
224 tas(volatile slock_t *lock)
225 {
226  register slock_t _res = 1;
227 
228  __asm__ __volatile__(
229  " lock \n"
230  " xchgb %0,%1 \n"
231 : "+q"(_res), "+m"(*lock)
232 : /* no inputs */
233 : "memory", "cc");
234  return (int) _res;
235 }
236 
237 #define SPIN_DELAY() spin_delay()
238 
239 static __inline__ void
240 spin_delay(void)
241 {
242  /*
243  * Adding a PAUSE in the spin delay loop is demonstrably a no-op on
244  * Opteron, but it may be of some use on EM64T, so we keep it.
245  */
246  __asm__ __volatile__(
247  " rep; nop \n");
248 }
249 
250 #endif /* __x86_64__ */
251 
252 
253 #if defined(__ia64__) || defined(__ia64)
254 /*
255  * Intel Itanium, gcc or Intel's compiler.
256  *
257  * Itanium has weak memory ordering, but we rely on the compiler to enforce
258  * strict ordering of accesses to volatile data. In particular, while the
259  * xchg instruction implicitly acts as a memory barrier with 'acquire'
260  * semantics, we do not have an explicit memory fence instruction in the
261  * S_UNLOCK macro. We use a regular assignment to clear the spinlock, and
262  * trust that the compiler marks the generated store instruction with the
263  * ".rel" opcode.
264  *
265  * Testing shows that assumption to hold on gcc, although I could not find
266  * any explicit statement on that in the gcc manual. In Intel's compiler,
267  * the -m[no-]serialize-volatile option controls that, and testing shows that
268  * it is enabled by default.
269  *
270  * While icc accepts gcc asm blocks on x86[_64], this is not true on ia64
271  * (at least not in icc versions before 12.x). So we have to carry a separate
272  * compiler-intrinsic-based implementation for it.
273  */
274 #define HAS_TEST_AND_SET
275 
276 typedef unsigned int slock_t;
277 
278 #define TAS(lock) tas(lock)
279 
280 /* On IA64, it's a win to use a non-locking test before the xchg proper */
281 #define TAS_SPIN(lock) (*(lock) ? 1 : TAS(lock))
282 
283 #ifndef __INTEL_COMPILER
284 
285 static __inline__ int
286 tas(volatile slock_t *lock)
287 {
288  long int ret;
289 
290  __asm__ __volatile__(
291  " xchg4 %0=%1,%2 \n"
292 : "=r"(ret), "+m"(*lock)
293 : "r"(1)
294 : "memory");
295  return (int) ret;
296 }
297 
298 #else /* __INTEL_COMPILER */
299 
300 static __inline__ int
301 tas(volatile slock_t *lock)
302 {
303  int ret;
304 
305  ret = _InterlockedExchange(lock,1); /* this is a xchg asm macro */
306 
307  return ret;
308 }
309 
310 /* icc can't use the regular gcc S_UNLOCK() macro either in this case */
311 #define S_UNLOCK(lock) \
312  do { __memory_barrier(); *(lock) = 0; } while (0)
313 
314 #endif /* __INTEL_COMPILER */
315 #endif /* __ia64__ || __ia64 */
316 
317 
318 /*
319  * On ARM and ARM64, we use __sync_lock_test_and_set(int *, int) if available.
320  *
321  * We use the int-width variant of the builtin because it works on more chips
322  * than other widths.
323  */
324 #if defined(__arm__) || defined(__arm) || defined(__aarch64__) || defined(__aarch64)
325 #ifdef HAVE_GCC__SYNC_INT32_TAS
326 #define HAS_TEST_AND_SET
327 
328 #define TAS(lock) tas(lock)
329 
330 typedef int slock_t;
331 
332 static __inline__ int
333 tas(volatile slock_t *lock)
334 {
335  return __sync_lock_test_and_set(lock, 1);
336 }
337 
338 #define S_UNLOCK(lock) __sync_lock_release(lock)
339 
340 /*
341  * Using an ISB instruction to delay in spinlock loops appears beneficial on
342  * high-core-count ARM64 processors. It seems mostly a wash for smaller gear,
343  * and ISB doesn't exist at all on pre-v7 ARM chips.
344  */
345 #if defined(__aarch64__) || defined(__aarch64)
346 
347 #define SPIN_DELAY() spin_delay()
348 
349 static __inline__ void
350 spin_delay(void)
351 {
352  __asm__ __volatile__(
353  " isb; \n");
354 }
355 
356 #endif /* __aarch64__ || __aarch64 */
357 #endif /* HAVE_GCC__SYNC_INT32_TAS */
358 #endif /* __arm__ || __arm || __aarch64__ || __aarch64 */
359 
360 
361 /*
362  * RISC-V likewise uses __sync_lock_test_and_set(int *, int) if available.
363  */
364 #if defined(__riscv)
365 #ifdef HAVE_GCC__SYNC_INT32_TAS
366 #define HAS_TEST_AND_SET
367 
368 #define TAS(lock) tas(lock)
369 
370 typedef int slock_t;
371 
372 static __inline__ int
373 tas(volatile slock_t *lock)
374 {
375  return __sync_lock_test_and_set(lock, 1);
376 }
377 
378 #define S_UNLOCK(lock) __sync_lock_release(lock)
379 
380 #endif /* HAVE_GCC__SYNC_INT32_TAS */
381 #endif /* __riscv */
382 
383 
384 /* S/390 and S/390x Linux (32- and 64-bit zSeries) */
385 #if defined(__s390__) || defined(__s390x__)
386 #define HAS_TEST_AND_SET
387 
388 typedef unsigned int slock_t;
389 
390 #define TAS(lock) tas(lock)
391 
392 static __inline__ int
393 tas(volatile slock_t *lock)
394 {
395  int _res = 0;
396 
397  __asm__ __volatile__(
398  " cs %0,%3,0(%2) \n"
399 : "+d"(_res), "+m"(*lock)
400 : "a"(lock), "d"(1)
401 : "memory", "cc");
402  return _res;
403 }
404 
405 #endif /* __s390__ || __s390x__ */
406 
407 
408 #if defined(__sparc__) /* Sparc */
409 /*
410  * Solaris has always run sparc processors in TSO (total store) mode, but
411  * linux didn't use to and the *BSDs still don't. So, be careful about
412  * acquire/release semantics. The CPU will treat superfluous membars as
413  * NOPs, so it's just code space.
414  */
415 #define HAS_TEST_AND_SET
416 
417 typedef unsigned char slock_t;
418 
419 #define TAS(lock) tas(lock)
420 
421 static __inline__ int
422 tas(volatile slock_t *lock)
423 {
424  register slock_t _res;
425 
426  /*
427  * See comment in src/backend/port/tas/sunstudio_sparc.s for why this
428  * uses "ldstub", and that file uses "cas". gcc currently generates
429  * sparcv7-targeted binaries, so "cas" use isn't possible.
430  */
431  __asm__ __volatile__(
432  " ldstub [%2], %0 \n"
433 : "=r"(_res), "+m"(*lock)
434 : "r"(lock)
435 : "memory");
436 #if defined(__sparcv7) || defined(__sparc_v7__)
437  /*
438  * No stbar or membar available, luckily no actually produced hardware
439  * requires a barrier.
440  */
441 #elif defined(__sparcv8) || defined(__sparc_v8__)
442  /* stbar is available (and required for both PSO, RMO), membar isn't */
443  __asm__ __volatile__ ("stbar \n":::"memory");
444 #else
445  /*
446  * #LoadStore (RMO) | #LoadLoad (RMO) together are the appropriate acquire
447  * barrier for sparcv8+ upwards.
448  */
449  __asm__ __volatile__ ("membar #LoadStore | #LoadLoad \n":::"memory");
450 #endif
451  return (int) _res;
452 }
453 
454 #if defined(__sparcv7) || defined(__sparc_v7__)
455 /*
456  * No stbar or membar available, luckily no actually produced hardware
457  * requires a barrier. We fall through to the default gcc definition of
458  * S_UNLOCK in this case.
459  */
460 #elif defined(__sparcv8) || defined(__sparc_v8__)
461 /* stbar is available (and required for both PSO, RMO), membar isn't */
462 #define S_UNLOCK(lock) \
463 do \
464 { \
465  __asm__ __volatile__ ("stbar \n":::"memory"); \
466  *((volatile slock_t *) (lock)) = 0; \
467 } while (0)
468 #else
469 /*
470  * #LoadStore (RMO) | #StoreStore (RMO, PSO) together are the appropriate
471  * release barrier for sparcv8+ upwards.
472  */
473 #define S_UNLOCK(lock) \
474 do \
475 { \
476  __asm__ __volatile__ ("membar #LoadStore | #StoreStore \n":::"memory"); \
477  *((volatile slock_t *) (lock)) = 0; \
478 } while (0)
479 #endif
480 
481 #endif /* __sparc__ */
482 
483 
484 /* PowerPC */
485 #if defined(__ppc__) || defined(__powerpc__) || defined(__ppc64__) || defined(__powerpc64__)
486 #define HAS_TEST_AND_SET
487 
488 typedef unsigned int slock_t;
489 
490 #define TAS(lock) tas(lock)
491 
492 /* On PPC, it's a win to use a non-locking test before the lwarx */
493 #define TAS_SPIN(lock) (*(lock) ? 1 : TAS(lock))
494 
495 /*
496  * The second operand of addi can hold a constant zero or a register number,
497  * hence constraint "=&b" to avoid allocating r0. "b" stands for "address
498  * base register"; most operands having this register-or-zero property are
499  * address bases, e.g. the second operand of lwax.
500  *
501  * NOTE: per the Enhanced PowerPC Architecture manual, v1.0 dated 7-May-2002,
502  * an isync is a sufficient synchronization barrier after a lwarx/stwcx loop.
503  * On newer machines, we can use lwsync instead for better performance.
504  *
505  * Ordinarily, we'd code the branches here using GNU-style local symbols, that
506  * is "1f" referencing "1:" and so on. But some people run gcc on AIX with
507  * IBM's assembler as backend, and IBM's assembler doesn't do local symbols.
508  * So hand-code the branch offsets; fortunately, all PPC instructions are
509  * exactly 4 bytes each, so it's not too hard to count.
510  */
511 static __inline__ int
512 tas(volatile slock_t *lock)
513 {
514  slock_t _t;
515  int _res;
516 
517  __asm__ __volatile__(
518 #ifdef USE_PPC_LWARX_MUTEX_HINT
519 " lwarx %0,0,%3,1 \n"
520 #else
521 " lwarx %0,0,%3 \n"
522 #endif
523 " cmpwi %0,0 \n"
524 " bne $+16 \n" /* branch to li %1,1 */
525 " addi %0,%0,1 \n"
526 " stwcx. %0,0,%3 \n"
527 " beq $+12 \n" /* branch to lwsync/isync */
528 " li %1,1 \n"
529 " b $+12 \n" /* branch to end of asm sequence */
530 #ifdef USE_PPC_LWSYNC
531 " lwsync \n"
532 #else
533 " isync \n"
534 #endif
535 " li %1,0 \n"
536 
537 : "=&b"(_t), "=r"(_res), "+m"(*lock)
538 : "r"(lock)
539 : "memory", "cc");
540  return _res;
541 }
542 
543 /*
544  * PowerPC S_UNLOCK is almost standard but requires a "sync" instruction.
545  * On newer machines, we can use lwsync instead for better performance.
546  */
547 #ifdef USE_PPC_LWSYNC
548 #define S_UNLOCK(lock) \
549 do \
550 { \
551  __asm__ __volatile__ (" lwsync \n" ::: "memory"); \
552  *((volatile slock_t *) (lock)) = 0; \
553 } while (0)
554 #else
555 #define S_UNLOCK(lock) \
556 do \
557 { \
558  __asm__ __volatile__ (" sync \n" ::: "memory"); \
559  *((volatile slock_t *) (lock)) = 0; \
560 } while (0)
561 #endif /* USE_PPC_LWSYNC */
562 
563 #endif /* powerpc */
564 
565 
566 /* Linux Motorola 68k */
567 #if (defined(__mc68000__) || defined(__m68k__)) && defined(__linux__)
568 #define HAS_TEST_AND_SET
569 
570 typedef unsigned char slock_t;
571 
572 #define TAS(lock) tas(lock)
573 
574 static __inline__ int
575 tas(volatile slock_t *lock)
576 {
577  register int rv;
578 
579  __asm__ __volatile__(
580  " clrl %0 \n"
581  " tas %1 \n"
582  " sne %0 \n"
583 : "=d"(rv), "+m"(*lock)
584 : /* no inputs */
585 : "memory", "cc");
586  return rv;
587 }
588 
589 #endif /* (__mc68000__ || __m68k__) && __linux__ */
590 
591 
592 /* Motorola 88k */
593 #if defined(__m88k__)
594 #define HAS_TEST_AND_SET
595 
596 typedef unsigned int slock_t;
597 
598 #define TAS(lock) tas(lock)
599 
600 static __inline__ int
601 tas(volatile slock_t *lock)
602 {
603  register slock_t _res = 1;
604 
605  __asm__ __volatile__(
606  " xmem %0, %2, %%r0 \n"
607 : "+r"(_res), "+m"(*lock)
608 : "r"(lock)
609 : "memory");
610  return (int) _res;
611 }
612 
613 #endif /* __m88k__ */
614 
615 
616 /*
617  * VAXen -- even multiprocessor ones
618  * (thanks to Tom Ivar Helbekkmo)
619  */
620 #if defined(__vax__)
621 #define HAS_TEST_AND_SET
622 
623 typedef unsigned char slock_t;
624 
625 #define TAS(lock) tas(lock)
626 
627 static __inline__ int
628 tas(volatile slock_t *lock)
629 {
630  register int _res;
631 
632  __asm__ __volatile__(
633  " movl $1, %0 \n"
634  " bbssi $0, (%2), 1f \n"
635  " clrl %0 \n"
636  "1: \n"
637 : "=&r"(_res), "+m"(*lock)
638 : "r"(lock)
639 : "memory");
640  return _res;
641 }
642 
643 #endif /* __vax__ */
644 
645 
646 #if defined(__mips__) && !defined(__sgi) /* non-SGI MIPS */
647 #define HAS_TEST_AND_SET
648 
649 typedef unsigned int slock_t;
650 
651 #define TAS(lock) tas(lock)
652 
653 /*
654  * Original MIPS-I processors lacked the LL/SC instructions, but if we are
655  * so unfortunate as to be running on one of those, we expect that the kernel
656  * will handle the illegal-instruction traps and emulate them for us. On
657  * anything newer (and really, MIPS-I is extinct) LL/SC is the only sane
658  * choice because any other synchronization method must involve a kernel
659  * call. Unfortunately, many toolchains still default to MIPS-I as the
660  * codegen target; if the symbol __mips shows that that's the case, we
661  * have to force the assembler to accept LL/SC.
662  *
663  * R10000 and up processors require a separate SYNC, which has the same
664  * issues as LL/SC.
665  */
666 #if __mips < 2
667 #define MIPS_SET_MIPS2 " .set mips2 \n"
668 #else
669 #define MIPS_SET_MIPS2
670 #endif
671 
672 static __inline__ int
673 tas(volatile slock_t *lock)
674 {
675  register volatile slock_t *_l = lock;
676  register int _res;
677  register int _tmp;
678 
679  __asm__ __volatile__(
680  " .set push \n"
681  MIPS_SET_MIPS2
682  " .set noreorder \n"
683  " .set nomacro \n"
684  " ll %0, %2 \n"
685  " or %1, %0, 1 \n"
686  " sc %1, %2 \n"
687  " xori %1, 1 \n"
688  " or %0, %0, %1 \n"
689  " sync \n"
690  " .set pop "
691 : "=&r" (_res), "=&r" (_tmp), "+R" (*_l)
692 : /* no inputs */
693 : "memory");
694  return _res;
695 }
696 
697 /* MIPS S_UNLOCK is almost standard but requires a "sync" instruction */
698 #define S_UNLOCK(lock) \
699 do \
700 { \
701  __asm__ __volatile__( \
702  " .set push \n" \
703  MIPS_SET_MIPS2 \
704  " .set noreorder \n" \
705  " .set nomacro \n" \
706  " sync \n" \
707  " .set pop " \
708 : /* no outputs */ \
709 : /* no inputs */ \
710 : "memory"); \
711  *((volatile slock_t *) (lock)) = 0; \
712 } while (0)
713 
714 #endif /* __mips__ && !__sgi */
715 
716 
717 #if defined(__m32r__) && defined(HAVE_SYS_TAS_H) /* Renesas' M32R */
718 #define HAS_TEST_AND_SET
719 
720 #include <sys/tas.h>
721 
722 typedef int slock_t;
723 
724 #define TAS(lock) tas(lock)
725 
726 #endif /* __m32r__ */
727 
728 
729 #if defined(__sh__) /* Renesas' SuperH */
730 #define HAS_TEST_AND_SET
731 
732 typedef unsigned char slock_t;
733 
734 #define TAS(lock) tas(lock)
735 
736 static __inline__ int
737 tas(volatile slock_t *lock)
738 {
739  register int _res;
740 
741  /*
742  * This asm is coded as if %0 could be any register, but actually SuperH
743  * restricts the target of xor-immediate to be R0. That's handled by
744  * the "z" constraint on _res.
745  */
746  __asm__ __volatile__(
747  " tas.b @%2 \n"
748  " movt %0 \n"
749  " xor #1,%0 \n"
750 : "=z"(_res), "+m"(*lock)
751 : "r"(lock)
752 : "memory", "t");
753  return _res;
754 }
755 
756 #endif /* __sh__ */
757 
758 
759 /* These live in s_lock.c, but only for gcc */
760 
761 
762 #if defined(__m68k__) && !defined(__linux__) /* non-Linux Motorola 68k */
763 #define HAS_TEST_AND_SET
764 
765 typedef unsigned char slock_t;
766 #endif
767 
768 /*
769  * Default implementation of S_UNLOCK() for gcc/icc.
770  *
771  * Note that this implementation is unsafe for any platform that can reorder
772  * a memory access (either load or store) after a following store. That
773  * happens not to be possible on x86 and most legacy architectures (some are
774  * single-processor!), but many modern systems have weaker memory ordering.
775  * Those that do must define their own version of S_UNLOCK() rather than
776  * relying on this one.
777  */
778 #if !defined(S_UNLOCK)
779 #define S_UNLOCK(lock) \
780  do { __asm__ __volatile__("" : : : "memory"); *(lock) = 0; } while (0)
781 #endif
782 
783 #endif /* defined(__GNUC__) || defined(__INTEL_COMPILER) */
784 
785 
786 
787 /*
788  * ---------------------------------------------------------------------
789  * Platforms that use non-gcc inline assembly:
790  * ---------------------------------------------------------------------
791  */
792 
793 #if !defined(HAS_TEST_AND_SET) /* We didn't trigger above, let's try here */
794 
795 
796 #if defined(__hppa) || defined(__hppa__) /* HP PA-RISC, GCC and HP compilers */
797 /*
798  * HP's PA-RISC
799  *
800  * See src/backend/port/hpux/tas.c.template for details about LDCWX. Because
801  * LDCWX requires a 16-byte-aligned address, we declare slock_t as a 16-byte
802  * struct. The active word in the struct is whichever has the aligned address;
803  * the other three words just sit at -1.
804  *
805  * When using gcc, we can inline the required assembly code.
806  */
807 #define HAS_TEST_AND_SET
808 
809 typedef struct
810 {
811  int sema[4];
812 } slock_t;
813 
814 #define TAS_ACTIVE_WORD(lock) ((volatile int *) (((uintptr_t) (lock) + 15) & ~15))
815 
816 #if defined(__GNUC__)
817 
818 static __inline__ int
819 tas(volatile slock_t *lock)
820 {
821  volatile int *lockword = TAS_ACTIVE_WORD(lock);
822  register int lockval;
823 
824  __asm__ __volatile__(
825  " ldcwx 0(0,%2),%0 \n"
826 : "=r"(lockval), "+m"(*lockword)
827 : "r"(lockword)
828 : "memory");
829  return (lockval == 0);
830 }
831 
832 /*
833  * The hppa implementation doesn't follow the rules of this files and provides
834  * a gcc specific implementation outside of the above defined(__GNUC__). It
835  * does so to avoid duplication between the HP compiler and gcc. So undefine
836  * the generic fallback S_UNLOCK from above.
837  */
838 #ifdef S_UNLOCK
839 #undef S_UNLOCK
840 #endif
841 #define S_UNLOCK(lock) \
842  do { \
843  __asm__ __volatile__("" : : : "memory"); \
844  *TAS_ACTIVE_WORD(lock) = -1; \
845  } while (0)
846 
847 #endif /* __GNUC__ */
848 
849 #define S_INIT_LOCK(lock) \
850  do { \
851  volatile slock_t *lock_ = (lock); \
852  lock_->sema[0] = -1; \
853  lock_->sema[1] = -1; \
854  lock_->sema[2] = -1; \
855  lock_->sema[3] = -1; \
856  } while (0)
857 
858 #define S_LOCK_FREE(lock) (*TAS_ACTIVE_WORD(lock) != 0)
859 
860 #endif /* __hppa || __hppa__ */
861 
862 
863 #if defined(__hpux) && defined(__ia64) && !defined(__GNUC__)
864 /*
865  * HP-UX on Itanium, non-gcc/icc compiler
866  *
867  * We assume that the compiler enforces strict ordering of loads/stores on
868  * volatile data (see comments on the gcc-version earlier in this file).
869  * Note that this assumption does *not* hold if you use the
870  * +Ovolatile=__unordered option on the HP-UX compiler, so don't do that.
871  *
872  * See also Implementing Spinlocks on the Intel Itanium Architecture and
873  * PA-RISC, by Tor Ekqvist and David Graves, for more information. As of
874  * this writing, version 1.0 of the manual is available at:
875  * http://h21007.www2.hp.com/portal/download/files/unprot/itanium/spinlocks.pdf
876  */
877 #define HAS_TEST_AND_SET
878 
879 typedef unsigned int slock_t;
880 
881 #include <ia64/sys/inline.h>
882 #define TAS(lock) _Asm_xchg(_SZ_W, lock, 1, _LDHINT_NONE)
883 /* On IA64, it's a win to use a non-locking test before the xchg proper */
884 #define TAS_SPIN(lock) (*(lock) ? 1 : TAS(lock))
885 #define S_UNLOCK(lock) \
886  do { _Asm_mf(); (*(lock)) = 0; } while (0)
887 
888 #endif /* HPUX on IA64, non gcc/icc */
889 
890 #if defined(_AIX) /* AIX */
891 /*
892  * AIX (POWER)
893  */
894 #define HAS_TEST_AND_SET
895 
896 #include <sys/atomic_op.h>
897 
898 typedef int slock_t;
899 
900 #define TAS(lock) _check_lock((slock_t *) (lock), 0, 1)
901 #define S_UNLOCK(lock) _clear_lock((slock_t *) (lock), 0)
902 #endif /* _AIX */
903 
904 
905 /* These are in sunstudio_(sparc|x86).s */
906 
907 #if defined(__SUNPRO_C) && (defined(__i386) || defined(__x86_64__) || defined(__sparc__) || defined(__sparc))
908 #define HAS_TEST_AND_SET
909 
910 #if defined(__i386) || defined(__x86_64__) || defined(__sparcv9) || defined(__sparcv8plus)
911 typedef unsigned int slock_t;
912 #else
913 typedef unsigned char slock_t;
914 #endif
915 
916 extern slock_t pg_atomic_cas(volatile slock_t *lock, slock_t with,
917  slock_t cmp);
918 
919 #define TAS(a) (pg_atomic_cas((a), 1, 0) != 0)
920 #endif
921 
922 
923 #ifdef _MSC_VER
924 typedef LONG slock_t;
925 
926 #define HAS_TEST_AND_SET
927 #define TAS(lock) (InterlockedCompareExchange(lock, 1, 0))
928 
929 #define SPIN_DELAY() spin_delay()
930 
931 /* If using Visual C++ on Win64, inline assembly is unavailable.
932  * Use a _mm_pause intrinsic instead of rep nop.
933  */
934 #if defined(_WIN64)
935 static __forceinline void
936 spin_delay(void)
937 {
938  _mm_pause();
939 }
940 #else
941 static __forceinline void
942 spin_delay(void)
943 {
944  /* See comment for gcc code. Same code, MASM syntax */
945  __asm rep nop;
946 }
947 #endif
948 
949 #include <intrin.h>
950 #pragma intrinsic(_ReadWriteBarrier)
951 
952 #define S_UNLOCK(lock) \
953  do { _ReadWriteBarrier(); (*(lock)) = 0; } while (0)
954 
955 #endif
956 
957 
958 #endif /* !defined(HAS_TEST_AND_SET) */
959 
960 
961 /* Blow up if we didn't have any way to do spinlocks */
962 #ifndef HAS_TEST_AND_SET
963 #error PostgreSQL does not have native spinlock support on this platform. To continue the compilation, rerun configure using --disable-spinlocks. However, performance will be poor. Please report this to pgsql-bugs@lists.postgresql.org.
964 #endif
965 
966 
967 #else /* !HAVE_SPINLOCKS */
968 
969 
970 /*
971  * Fake spinlock implementation using semaphores --- slow and prone
972  * to fall foul of kernel limits on number of semaphores, so don't use this
973  * unless you must! The subroutines appear in spin.c.
974  */
975 typedef int slock_t;
976 
977 extern bool s_lock_free_sema(volatile slock_t *lock);
978 extern void s_unlock_sema(volatile slock_t *lock);
979 extern void s_init_lock_sema(volatile slock_t *lock, bool nested);
980 extern int tas_sema(volatile slock_t *lock);
981 
982 #define S_LOCK_FREE(lock) s_lock_free_sema(lock)
983 #define S_UNLOCK(lock) s_unlock_sema(lock)
984 #define S_INIT_LOCK(lock) s_init_lock_sema(lock, false)
985 #define TAS(lock) tas_sema(lock)
986 
987 
988 #endif /* HAVE_SPINLOCKS */
989 
990 
991 /*
992  * Default Definitions - override these above as needed.
993  */
994 
995 #if !defined(S_LOCK)
996 #define S_LOCK(lock) \
997  (TAS(lock) ? s_lock((lock), __FILE__, __LINE__, PG_FUNCNAME_MACRO) : 0)
998 #endif /* S_LOCK */
999 
1000 #if !defined(S_LOCK_FREE)
1001 #define S_LOCK_FREE(lock) (*(lock) == 0)
1002 #endif /* S_LOCK_FREE */
1003 
1004 #if !defined(S_UNLOCK)
1005 /*
1006  * Our default implementation of S_UNLOCK is essentially *(lock) = 0. This
1007  * is unsafe if the platform can reorder a memory access (either load or
1008  * store) after a following store; platforms where this is possible must
1009  * define their own S_UNLOCK. But CPU reordering is not the only concern:
1010  * if we simply defined S_UNLOCK() as an inline macro, the compiler might
1011  * reorder instructions from inside the critical section to occur after the
1012  * lock release. Since the compiler probably can't know what the external
1013  * function s_unlock is doing, putting the same logic there should be adequate.
1014  * A sufficiently-smart globally optimizing compiler could break that
1015  * assumption, though, and the cost of a function call for every spinlock
1016  * release may hurt performance significantly, so we use this implementation
1017  * only for platforms where we don't know of a suitable intrinsic. For the
1018  * most part, those are relatively obscure platform/compiler combinations to
1019  * which the PostgreSQL project does not have access.
1020  */
1021 #define USE_DEFAULT_S_UNLOCK
1022 extern void s_unlock(volatile slock_t *lock);
1023 #define S_UNLOCK(lock) s_unlock(lock)
1024 #endif /* S_UNLOCK */
1025 
1026 #if !defined(S_INIT_LOCK)
1027 #define S_INIT_LOCK(lock) S_UNLOCK(lock)
1028 #endif /* S_INIT_LOCK */
1029 
1030 #if !defined(SPIN_DELAY)
1031 #define SPIN_DELAY() ((void) 0)
1032 #endif /* SPIN_DELAY */
1033 
1034 #if !defined(TAS)
1035 extern int tas(volatile slock_t *lock); /* in port/.../tas.s, or
1036  * s_lock.c */
1037 
1038 #define TAS(lock) tas(lock)
1039 #endif /* TAS */
1040 
1041 #if !defined(TAS_SPIN)
1042 #define TAS_SPIN(lock) TAS(lock)
1043 #endif /* TAS_SPIN */
1044 
1046 
1047 /*
1048  * Platform-independent out-of-line support routines
1049  */
1050 extern int s_lock(volatile slock_t *lock, const char *file, int line, const char *func);
1051 
1052 /* Support for dynamic adjustment of spins_per_delay */
1053 #define DEFAULT_SPINS_PER_DELAY 100
1054 
1055 extern void set_spins_per_delay(int shared_spins_per_delay);
1056 extern int update_spins_per_delay(int shared_spins_per_delay);
1057 
1058 /*
1059  * Support for spin delay which is useful in various places where
1060  * spinlock-like procedures take place.
1061  */
1062 typedef struct
1063 {
1064  int spins;
1065  int delays;
1067  const char *file;
1068  int line;
1069  const char *func;
1070 } SpinDelayStatus;
1071 
1072 static inline void
1074  const char *file, int line, const char *func)
1075 {
1076  status->spins = 0;
1077  status->delays = 0;
1078  status->cur_delay = 0;
1079  status->file = file;
1080  status->line = line;
1081  status->func = func;
1082 }
1083 
1084 #define init_local_spin_delay(status) init_spin_delay(status, __FILE__, __LINE__, PG_FUNCNAME_MACRO)
1087 
1088 #endif /* S_LOCK_H */
#define PGDLLIMPORT
Definition: c.h:1331
static void static void status(const char *fmt,...) pg_attribute_printf(1
Definition: pg_regress.c:229
static int cmp(const chr *x, const chr *y, size_t len)
Definition: regc_locale.c:747
void set_spins_per_delay(int shared_spins_per_delay)
Definition: s_lock.c:196
void perform_spin_delay(SpinDelayStatus *status)
Definition: s_lock.c:125
int tas_sema(volatile slock_t *lock)
Definition: spin.c:170
void s_unlock_sema(volatile slock_t *lock)
Definition: spin.c:152
static void init_spin_delay(SpinDelayStatus *status, const char *file, int line, const char *func)
Definition: s_lock.h:1073
void finish_spin_delay(SpinDelayStatus *status)
Definition: s_lock.c:175
int slock_t
Definition: s_lock.h:975
int s_lock(volatile slock_t *lock, const char *file, int line, const char *func)
Definition: s_lock.c:92
PGDLLIMPORT slock_t dummy_spinlock
Definition: s_lock.c:64
void s_init_lock_sema(volatile slock_t *lock, bool nested)
Definition: spin.c:121
int update_spins_per_delay(int shared_spins_per_delay)
Definition: s_lock.c:207
bool s_lock_free_sema(volatile slock_t *lock)
Definition: spin.c:162
const char * file
Definition: s_lock.h:1067
const char * func
Definition: s_lock.h:1069